> 3.15.4 | Digital Audio Interface (DAI)

> The DAI can be used to connect audio devices capable of PCM (Pulse Code Modulation) or for type approval. The following chapters describe the PCM interface functionality.
> The PCM functionality allows the use of a codec like for example the MC145483. This codec replaces the analog audio inputs and outputs during a call, if digital audio is selected by AT^SAIC. The PCM interface is configurable with the AT^SAIC command (see [1]) and supports the following features:

> • | Master and slave mode

> • | Short frame and long frame synchronization

> • | 256 kHz or 512 kHz bit clock frequency

> For the PCM interface configuration the parameters <clock>, <mode> and <framemode> of the AT^SAIC command are used. The following table lists possible combinations:

> Table 17: | Configuration combinations for the PCM interface

> Configuration | <clock> | <mode> | <framemode>
> Master, 256kHz, short frame | 0 | 0 | 0
> Master, 256kHz, long frame | 0 | 0 | 1
> Master, 512kHz, short frame | 1 | 0 | 0
> Master, 512kHz, long frame | 1 | 0 | 1
> Slave, 256kHz, short frame | 0 or 11 | 1 | 0
> Slave, 256kHz, long frame | 0 or 1 | 1 | 1
> Slave, 512kHz, short frame | 0 or 1 | 1 | 0
> Slave, 512kHz, long frame | 0 or 1 | 1 | 1

> 1
> In slave mode the BCLKIN signal is directly used for data shifting. Therefore, the clock frequency setting is not evaluated and may be either 0 or 1.
> In all configurations the PCM interface has the following common features:

> • | 16 Bit linear

> • | 8 kHz sample rate

> • | the most significant bit MSB is transferred first

> • | 125 µs frame duration

> • | common frame sync signal for transmit and receive

> Table 18 shows the assignment of the DAI0...6 pins to the PCM interface signals. To avoid hardware conflicts different pins are used as inputs and outputs for frame sync and clock signals in master or slave operation. The table shows also which pin is used for master or slave. The data pins (TXDAI and RXDAI) however are used in both modes. Unused inputs have to be tied to GND, unused outputs must be left open.

> Table 18: | Overview of DAI pin functions

> Signal name on B2B connector | Function for PCM Interface | Input/Output
> DAI0 | TXDAI | Master/Slave | O
> DAI1 | RXDAI | Master/Slave | I
> DAI2 | FS (Frame sync) | Master | O
> DAI3 | BITCLK | Master | O
> DAI4 | FSIN | Slave | I
> DAI5 | BCLKIN | Slave | I
> DAI6 | nc |  | I

> 3.15.4.1 | Master Mode

> To clock input and output PCM samples the PCM interface delivers a bit clock (BITCLK) which is synchronous to the GSM system clock. The frequency of the bit clock is 256kHz or 512kHz. Any edge of this clock deviates less than ±100ns (Jitter) from an ideal 256kHz clock respectively deviates less than ±320ns from an ideal 512kHz clock.
> The frame sync signal (FS) has a frequency of 8kHz and is high for one BITCLK period before the data transmission starts if short frame is configured. If long frame is selected the frame sync signal (FS) is high during the whole transfer of the 16 data bits. Each frame has a duration of 125µs and contains 32 respective 64 clock cycles.
> Figure 29: Master PCM interface Application
> The timing of a PCM short frame is shown in Figure 30. The 16-bit TXDAI and RXDAI data is transferred simultaneously in both directions during the first 16 clock cycles after the frame sync pulse. The duration of a frame sync pulse is one BITCLK period, starting at the rising edge of BITCLK. TXDAI data is shifted out at the next rising edge of BITCLK. RXDAI data (i.e. data transmitted from the host application to the module's RXDAI line) is sampled at the falling edge of BITCLK.
> Figure 30: Short Frame PCM timing
> The timing of a PCM long frame is shown in Figure 31. The 16-bit TXDAI and RXDAI data is transferred simultaneously in both directions while the frame sync pulse FS is high. For this reason the duration of a frame sync pulse is 16 BITCLK periods, starting at the rising edge of BITCLK. TXDAI data is shifted out at the same rising edge of BITCLK. RXDAI data (i.e. data transmitted from the host application to the module's RXDAI line) is sampled at the falling edge of BITCLK.
> Figure 31: Long Frame PCM timing

> 3.15.4.2 | Slave Mode

> In slave mode the PCM interface is controlled by an external bit clock and an external frame sync signal applied to the BCLKIN and FSIN pins and delivered either by the connected codec or another source. The bit clock frequency has to be in the range of 256kHz -125ppm to 512kHz +125ppm.
> Data transfer starts at the falling edge of FSIN if the short frame format is selected, and at the rising edge of FSIN if long frame format is selected. With this edge control the frame sync signal is independent of the frame sync pulse length.
> TXDAI data is shifted out at the rising edge of BCLKIN. RXDAI data (i.e. data transmitted from the host application to the module's RXDAI line) is sampled at the falling edge of BCLKIN.
> The deviation of the external frame rate from the internal frame rate must not exceed ±125ppm. The internal frame rate of nominal 8kHz is synchronized to the GSM network.
> The difference between the internal and the external frame rate is equalized by doubling or skipping samples. This happens for example every second, if the difference is 125ppm.
> The resulting distortion can be neglected in speech signals.
> The pins BITCLK and FS remain low in slave mode.
> Figure 32 shows the typical slave configuration. The external codec delivers the bit clock and the frame sync signal. If the codec itself is not able to run in master mode as for example the MC145483, a third party has to generate the clock and the frame sync signal.
> Figure 32: Slave PCM interface application
> The following figures show the slave short and long frame timings. Because these are edge controlled, frame sync signals may deviate from the ideally form as shown with the dotted lines.
> Figure 33: Slave PCM Timing, Short Frame selected
> Figure 34: Slave PCM Timing, Long Frame selected