> 3.1 | Master Mode

> To clock input and output PCM samples the PCM interface delivers a bit clock (BITCLK) which is synchronous to the GSM system clock. The frequency of the bit clock is 256kHz or 512kHz. Any edge of this clock deviates less than ±100ns (Jitter) from an ideal 256-kHz clock respectively deviates less than ±320ns from an ideal 512kHz clock.
> The frame sync signal (FS) has a frequency of 8 kHz and is high for one BITCLK period before the data transmission starts if short frame is configured. If long frame is selected the frame sync signal (FS) is high during the whole transfer of the 16 data bits. Each frame has a duration of 125µs and contains 32 respective 64 clock cycles.
> Figure 2: Master PCM interface Application
> The timing of a PCM short frame is shown in Figure 3. The 16-bit TXDAI and RXDAI data are transferred simultaneously in both directions during the first 16 clock cycles after the frame sync pulse. The duration of a frame sync pulse is one BITCLK period, starting at the rising edge of BITCLK. TXDAI data is shifted out at the next rising edge of BITCLK. RXDAI data (i.e. data transmitted from the host application to the module's RXDAI line) is sampled at the falling edge of BITCLK.
> Figure 3: Short Frame PCM timing
> The timing of a PCM long frame is shown in Figure 4. The 16-bit TXDAI and RXDAI data are transferred simultaneously in both directions while the frame sync pulse FS is high. For this reason the duration of a frame sync pulse is 16 BITCLK periods, starting at the rising edge of BITCLK. TXDAI data is shifted out at the same rising edge of BITCLK. RXDAI data (i.e. data transmitted from the host application to the module's RXDAI line) is sampled at the falling edge of BITCLK.
> Figure 4: Long Frame PCM timing