> 3.3.2 | Signal States after Startup

> Table 8 describes the various states each interface pin passes through after startup and during operation.
> As shown in Figure 5 and Figure 6 the pins are in undefined state while the module is initializing. Once the startup initialization has completed, i.e. when CTS is high and the software is running, all pins are in defined state. The state of several pins will change again once the respective interface is activated or configured by AT command:

> Table 8: | Signal States

> Signal name | Undefined state during startup1 | Defined state after initialization | Active state after configuration by AT command
> GPIO | SPI | I 2C | DAI
> SYNC | O, L | O, L |  |  |  |
> CCIN | Tri, PU(100k) | I, PU(100k) |  |  |  |
> CCRST | O, L | O, L |  |  |  |
> CCIO | O, L | O, L |  |  |  |
> CCCLK | O, L | O, L |  |  |  |
> CCVCC | O, L | 2.9V |  |  |  |
> RXD0 | Tri, PU | O, H |  |  |  |
> TXD0 | Tri, PU | I, PD(330k) |  |  |  |
> CTS0 | O, L | O, L 2 |  |  |  |
> RTS0 | Tri, PU | I, PD(330k) |  |  |  |
> DTR0 | Tri, PU | I |  |  |  |
> DCD0 | Tri | O, H |  |  |  |
> DSR0 | Tri | O, L 2 |  |  |  |
> RING0 | Tri, PU | O, H 3 |  |  |  |
> RXD1 | O, H | O, H |  |  |  |
> TXD1 | Tri, PD(330k) | I, PD(330k) |  |  |  |
> CTS1 | O, L | O, L 2 |  |  |  |
> RTS1 | Tri, PD(330k) | I, PD(330k) |  |  |  |
> SPIDI | Tri | Tri |  | I | Tri |
> SPICS | Tri | O, H |  | O, L | Tri |
> I2CDAT_SPIDO | Tri | Tri |  | O, L/H | IO |
> I2CCLK_SPICLK | Tri | Tri |  | O, L/H | O, OD |
> GPIO1 | Tri, PU | Tri | IO |  |  |
> GPIO2 | Tri, PU | Tri | IO |  |  |
> GPIO3 | Tri, PU | Tri | IO |  |  |
> GPIO4 | Tri, PD | Tri | IO |  |  |
> GPIO5 | O, L | Tri | IO |  |  |
> GPIO6 | Tri, PU | Tri | IO |  |  |
> GPIO7 | Tri, PU | Tri | IO |  |  |
> GPIO8 | O, L | Tri | IO |  |  |
> GPIO9 | Tri | Tri | IO |  |  |
> GPIO10 | Tri | Tri | IO |  |  |
> DAC_OUT | O, L | O, L |  |  |  |
> DAI0 | Tri | O, L |  |  |  | O, L
> DAI1 | Tri | Tri |  |  |  | I
> DAI2 | O, H | O, L 4 |  |  |  | O, L
> DAI3 | Tri | O, L |  |  |  | O, L
> DAI4 | Tri | Tri |  |  |  | I
> DAI5 | Tri | Tri |  |  |  | I
> DAI6 | Tri | Tri |  |  |  | I

> 1
> During the first 100µs after startup, glitches on the digital lines may occur. As a result, the digital lines may go through a high or low output state before entering the specified states.
> 2
> Before reaching the defined state the signal has the intermediate state O, H for about 2s.
> 3
> Before reaching the defined state the signal has the intermediate states O, H for about 2s and O, L for about 1s.
> 4
> Before reaching the defined state the signal has the intermediate state O, H for about 0.5s.
> Abbreviations used in Table 8:

> L = Low level H = High level L/H = Low or high level I = Input O = Output Tri = Tristate | OD = Open Drain PD = Pull down with min +15µA and max. +100µA PD(…k) = Fix pull down resistor PU = Pull up with min -15µA and max. -100µA PU(…k) = Fix pull up resistor