> 3.2 | Slave Mode

> In slave mode the PCM interface is controlled by the external bit clock and the external frame sync signal applied to the pins BCLKIN and FSIN and delivered either by the connected codes or another source. The bit clock frequency can be in the range of 256kHz -125ppm to 512kHz +125ppm.
> Data transfer starts at the falling edge of FSIN if the short frame format is selected, and at the rising edge of FSIN if long frame format is selected. With this edge control the frame sync signal is independent of the frame sync pulse length.
> TXDAI data is shifted out at the rising edge of BCLKIN. RXDAI data (i.e. data transmitted from the host application to the module's RXDAI line) is sampled at the falling edge of BCLKIN.
> The deviation of the external frame rate from the internal frame rate must not exceed ±125ppm. The internal frame rate of nominal 8kHz is synchronized to the GSM network.
> The difference between the internal and the external frame rate is equalized by doubling or skipping samples. This happens for example every second, if the difference is 125ppm.
> The resulting distortion can be neglected in speech signals.
> The pins BITCLK and FS remain low in slave mode.
> Figure 5 shows the typical slave configuration. The external codec delivers the bit clock and the frame sync signal. If the codec itself is not able to run in master mode as for example the MC145483, a third party has to generate the clock and the frame sync signal.
> Figure 5: Slave PCM interface application
> The following figures show the slave short and long frame timings. Because these are edge controlled, frame sync signals may deviate from the ideally form as shown with the dotted lines.
> Figure 6: Slave PCM Timing, Short Frame selected
> Figure 7: Slave PCM Timing, Long Frame selected